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Injectable PCB templates

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This commit is contained in:
Bán Dénes 2024-01-23 12:04:37 +01:00
parent 21e50cb11d
commit 6079aaf332
31 changed files with 277 additions and 251 deletions
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2
.gitignore vendored
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@ -117,4 +117,4 @@ dist
# Project specific
output
temp*
temp\b

2
src/ergogen.js
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@ -103,6 +103,8 @@ const inject = (type, name, value) => {
switch (type) {
case 'footprint':
return pcbs_lib.inject_footprint(name, value)
case 'template':
return pcbs_lib.inject_template(name, value)
default:
throw new Error(`Unknown injection type "${type}" with name "${name}" and value "${value}"!`)
}

10
src/io.js
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@ -28,6 +28,16 @@ exports.unpack = async (zip) => {
injections.push(['footprint', name, parsed])
}
// bundled pcb templates
const tpls = zip.folder('templates')
for (const tpl of tpls.file(/.*\.js$/)) {
const name = tpl.name.slice('templates/'.length).split('.')[0]
const text = await tpl.async('string')
const parsed = new Function(module_prefix + text + module_suffix)()
// TODO: some sort of template validation?
injections.push(['template', name, parsed])
}
return [config_text, injections]
}

147
src/pcbs.js
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@ -7,116 +7,6 @@ const prep = require('./prepare')
const anchor = require('./anchor').parse
const filter = require('./filter').parse
const kicad_prefix = `
(kicad_pcb (version 20171130) (host pcbnew 5.1.6)
(page A3)
(title_block
(title KEYBOARD_NAME_HERE)
(rev VERSION_HERE)
(company YOUR_NAME_HERE)
)
(general
(thickness 1.6)
)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
)
(setup
(last_trace_width 0.25)
(trace_clearance 0.2)
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.2)
(via_size 0.8)
(via_drill 0.4)
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(edge_width 0.05)
(segment_width 0.2)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.12)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.524 1.524)
(pad_drill 0.762)
(pad_to_mask_clearance 0.05)
(aux_axis_origin 0 0)
(visible_elements FFFFFF7F)
(pcbplotparams
(layerselection 0x010fc_ffffffff)
(usegerberextensions false)
(usegerberattributes true)
(usegerberadvancedattributes true)
(creategerberjobfile true)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
)
`
const kicad_suffix = `
)
`
const kicad_netclass = `
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
(via_dia 0.8)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
__ADD_NET
)
`
const makerjs2kicad = exports._makerjs2kicad = (model, layer) => {
const grs = []
const xy = val => `${val[0]} ${-val[1]}`
@ -148,11 +38,16 @@ const makerjs2kicad = exports._makerjs2kicad = (model, layer) => {
}
const footprint_types = require('./footprints')
const template_types = require('./templates')
exports.inject_footprint = (name, fp) => {
footprint_types[name] = fp
}
exports.inject_template = (name, t) => {
template_types[name] = t
}
const xy_obj = (x, y) => {
return {
x,
@ -300,8 +195,9 @@ exports.parse = (config, points, outlines, units) => {
for (const [pcb_name, pcb_config] of Object.entries(pcbs)) {
// config sanitization
a.unexpected(pcb_config, `pcbs.${pcb_name}`, ['outlines', 'footprints', 'references'])
a.unexpected(pcb_config, `pcbs.${pcb_name}`, ['outlines', 'footprints', 'references', 'template', 'params'])
const references = a.sane(pcb_config.references || false, `pcbs.${pcb_name}.references`, 'boolean')()
const template = template_types[a.in(pcb_config.template || 'kicad5', `pcbs.${pcb_name}.template`, Object.keys(template_types))]
// outline conversion
if (a.type(pcb_config.outlines)() == 'array') {
@ -358,28 +254,19 @@ exports.parse = (config, points, outlines, units) => {
// finalizing nets
const nets_arr = []
const add_nets_arr = []
for (const [net, index] of Object.entries(nets)) {
nets_arr.push(`(net ${index} "${net}")`)
add_nets_arr.push(`(add_net "${net}")`)
nets_arr.push(net_obj(net, index))
}
const netclass = kicad_netclass.replace('__ADD_NET', add_nets_arr.join('\n'))
const nets_text = nets_arr.join('\n')
const footprint_text = footprints.join('\n')
const outline_text = Object.values(kicad_outlines).join('\n')
const personalized_prefix = kicad_prefix
.replace('KEYBOARD_NAME_HERE', pcb_name)
.replace('VERSION_HERE', config.meta && config.meta.version || 'v1.0.0')
.replace('YOUR_NAME_HERE', config.meta && config.meta.author || 'Unknown')
results[pcb_name] = `
${personalized_prefix}
${nets_text}
${netclass}
${footprint_text}
${outline_text}
${kicad_suffix}
`
results[pcb_name] = template({
name: pcb_name,
version: config.meta && config.meta.version || 'v1.0.0',
author: config.meta && config.meta.author || 'Unknown',
nets: nets_arr,
footprints: footprints,
outlines: kicad_outlines,
custom: pcb_config.params
})
}
return results

3
src/templates/index.js Normal file
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@ -0,0 +1,3 @@
module.exports = {
kicad5: require('./kicad5')
}

121
src/templates/kicad5.js Normal file
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@ -0,0 +1,121 @@
module.exports = params => {
const net_text = params.nets.join('\n')
const netclass_text = params.nets.map(net => `(add_net "${net.name}")`).join('\n')
const footprint_text = params.footprints.join('\n')
const outline_text = Object.values(params.outlines).join('\n')
return `
(kicad_pcb (version 20171130) (host pcbnew 5.1.6)
(page A3)
(title_block
(title ${params.name})
(rev ${params.version})
(company ${params.author})
)
(general
(thickness 1.6)
)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
)
(setup
(last_trace_width 0.25)
(trace_clearance 0.2)
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.2)
(via_size 0.8)
(via_drill 0.4)
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(edge_width 0.05)
(segment_width 0.2)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.12)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.524 1.524)
(pad_drill 0.762)
(pad_to_mask_clearance 0.05)
(aux_axis_origin 0 0)
(visible_elements FFFFFF7F)
(pcbplotparams
(layerselection 0x010fc_ffffffff)
(usegerberextensions false)
(usegerberattributes true)
(usegerberadvancedattributes true)
(creategerberjobfile true)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
)
${net_text}
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
(via_dia 0.8)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
${netclass_text}
)
${footprint_text}
${outline_text}
)
`
}

13
test/cli/big/reference/pcbs/_export.kicad_pcb
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@ -1,5 +1,5 @@
(kicad_pcb (version 20171130) (host pcbnew 5.1.6)
(page A3)
@ -92,8 +92,8 @@
(outputdirectory ""))
)
(net 0 "")
(net 0 "")
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
@ -104,9 +104,8 @@
(add_net "")
)
)

13
test/cli/big/reference/pcbs/export.kicad_pcb
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@ -1,5 +1,5 @@
(kicad_pcb (version 20171130) (host pcbnew 5.1.6)
(page A3)
@ -92,8 +92,8 @@
(outputdirectory ""))
)
(net 0 "")
(net 0 "")
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
@ -104,9 +104,8 @@
(add_net "")
)
)

1
test/cli/bundle/reference/pcbs/custom_template.kicad_pcb Normal file
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@ -0,0 +1 @@
Custom template override. The secret is 42.

13
test/cli/bundle/reference/pcbs/pcb.kicad_pcb
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@ -1,5 +1,5 @@
(kicad_pcb (version 20171130) (host pcbnew 5.1.6)
(page A3)
@ -92,8 +92,8 @@
(outputdirectory ""))
)
(net 0 "")
(net 0 "")
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
@ -104,7 +104,7 @@
(add_net "")
)
(module injected_test_footprint (layer F.Cu) (tedit 5E1ADAC2)
(at 0 0 0)
@ -112,11 +112,10 @@
(fp_text reference "I1" (at 0 0) (layer F.SilkS) hide (effects (font (size 1.27 1.27) (thickness 0.15))))
)
(gr_line (start -9 9) (end 9 9) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start -9 9) (end 9 9) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 9 9) (end 9 -9) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 9 -9) (end -9 -9) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start -9 -9) (end -9 9) (angle 90) (layer Edge.Cuts) (width 0.15))
)

13
test/cli/medium/reference/pcbs/export.kicad_pcb
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@ -1,5 +1,5 @@
(kicad_pcb (version 20171130) (host pcbnew 5.1.6)
(page A3)
@ -92,8 +92,8 @@
(outputdirectory ""))
)
(net 0 "")
(net 0 "")
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
@ -104,9 +104,8 @@
(add_net "")
)
)

BIN
test/fixtures/bundle.zip vendored
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Binary file not shown.

5
test/fixtures/bundle/config.yaml vendored
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@ -11,3 +11,8 @@ pcbs:
injected:
what: injected
where: matrix
custom_template:
outlines.edge.outline: box
template: custom_template
params:
secret: 42

3
test/fixtures/bundle/templates/custom_template.js vendored Normal file
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@ -0,0 +1,3 @@
module.exports = params => {
return `Custom template override. The secret is ${params.custom.secret}.`
}

13
test/footprints/button___pcbs_pcb.kicad_pcb
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@ -1,5 +1,5 @@
(kicad_pcb (version 20171130) (host pcbnew 5.1.6)
(page A3)
@ -92,10 +92,10 @@
(outputdirectory ""))
)
(net 0 "")
(net 0 "")
(net 1 "from")
(net 2 "to")
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
@ -108,7 +108,7 @@
(add_net "to")
)
(module E73:SW_TACT_ALPS_SKQGABE010 (layer F.Cu) (tstamp 5BF2CC94)
@ -168,8 +168,7 @@
)
)

13
test/footprints/choc___pcbs_pcb.kicad_pcb
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@ -1,5 +1,5 @@
(kicad_pcb (version 20171130) (host pcbnew 5.1.6)
(page A3)
@ -92,10 +92,10 @@
(outputdirectory ""))
)
(net 0 "")
(net 0 "")
(net 1 "from")
(net 2 "to")
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
@ -108,7 +108,7 @@
(add_net "to")
)
(module PG1350 (layer F.Cu) (tedit 5DD50112)
(at 0 0 0)
@ -353,8 +353,7 @@
(pad 2 smd rect (at -8.275 -3.75 0) (size 2.6 2.6) (layers F.Cu F.Paste F.Mask) (net 2 "to"))
)
)

13
test/footprints/chocmini___pcbs_pcb.kicad_pcb
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@ -1,5 +1,5 @@
(kicad_pcb (version 20171130) (host pcbnew 5.1.6)
(page A3)
@ -92,10 +92,10 @@
(outputdirectory ""))
)
(net 0 "")
(net 0 "")
(net 1 "from")
(net 2 "to")
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
@ -108,7 +108,7 @@
(add_net "to")
)
(module lib:Kailh_PG1232 (layer F.Cu) (tedit 5E1ADAC2)
(at 0 0 0)
@ -328,8 +328,7 @@
)
)

13
test/footprints/diode___pcbs_pcb.kicad_pcb
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@ -1,5 +1,5 @@
(kicad_pcb (version 20171130) (host pcbnew 5.1.6)
(page A3)
@ -92,10 +92,10 @@
(outputdirectory ""))
)
(net 0 "")
(net 0 "")
(net 1 "from")
(net 2 "to")
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
@ -108,7 +108,7 @@
(add_net "to")
)
(module ComboDiode (layer F.Cu) (tedit 5B24D78E)
@ -147,8 +147,7 @@
)
)

13
test/footprints/mx___pcbs_pcb.kicad_pcb
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@ -1,5 +1,5 @@
(kicad_pcb (version 20171130) (host pcbnew 5.1.6)
(page A3)
@ -92,10 +92,10 @@
(outputdirectory ""))
)
(net 0 "")
(net 0 "")
(net 1 "from")
(net 2 "to")
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
@ -108,7 +108,7 @@
(add_net "to")
)
(module MX (layer F.Cu) (tedit 5DD4F656)
(at 0 0 0)
@ -353,8 +353,7 @@
(pad 2 smd rect (at -5.842 -5.08 0) (size 2.55 2.5) (layers F.Cu F.Paste F.Mask) (net 2 "to"))
)
)

13
test/footprints/pad___pcbs_pcb.kicad_pcb
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@ -1,5 +1,5 @@
(kicad_pcb (version 20171130) (host pcbnew 5.1.6)
(page A3)
@ -92,9 +92,9 @@
(outputdirectory ""))
)
(net 0 "")
(net 0 "")
(net 1 "net")
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
@ -106,7 +106,7 @@
(add_net "net")
)
(module SMDPad (layer F.Cu) (tedit 5B24D78E)
@ -219,8 +219,7 @@
)
)

13
test/footprints/promicro___pcbs_pcb.kicad_pcb
View file

@ -1,5 +1,5 @@
(kicad_pcb (version 20171130) (host pcbnew 5.1.6)
(page A3)
@ -92,7 +92,7 @@
(outputdirectory ""))
)
(net 0 "")
(net 0 "")
(net 1 "RAW")
(net 2 "GND")
(net 3 "RST")
@ -115,7 +115,7 @@
(net 20 "P7")
(net 21 "P8")
(net 22 "P9")
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
@ -148,7 +148,7 @@
(add_net "P9")
)
(module ProMicro (layer F.Cu) (tedit 5B307E4C)
(at 0 0 0)
@ -312,8 +312,7 @@
(pad 24 thru_hole circle (at 13.97 7.62 0) (size 1.7526 1.7526) (drill 1.0922) (layers *.Cu *.SilkS *.Mask) (net 22 "P9"))
)
)

13
test/footprints/rest___pcbs_pcb.kicad_pcb
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@ -1,5 +1,5 @@
(kicad_pcb (version 20171130) (host pcbnew 5.1.6)
(page A3)
@ -92,7 +92,7 @@
(outputdirectory ""))
)
(net 0 "")
(net 0 "")
(net 1 "from")
(net 2 "to")
(net 3 "pos")
@ -108,7 +108,7 @@
(net 13 "C")
(net 14 "D")
(net 15 "net")
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
@ -134,7 +134,7 @@
(add_net "net")
)
(module ALPS (layer F.Cu) (tedit 5CF31DEF)
@ -522,8 +522,7 @@
)
)

13
test/footprints/trrs___pcbs_pcb.kicad_pcb
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@ -1,5 +1,5 @@
(kicad_pcb (version 20171130) (host pcbnew 5.1.6)
(page A3)
@ -92,12 +92,12 @@
(outputdirectory ""))
)
(net 0 "")
(net 0 "")
(net 1 "A")
(net 2 "B")
(net 3 "C")
(net 4 "D")
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
@ -112,7 +112,7 @@
(add_net "D")
)
(module TRRS-PJ-320A-dual (layer F.Cu) (tedit 5970F8E5)
@ -221,8 +221,7 @@
(pad 4 thru_hole oval (at 0 3.2 0) (size 1.6 2.2) (drill oval 0.9 1.5) (layers *.Cu *.Mask) (net 4 "D"))
)
)

4
test/helpers/mock_footprints.js → test/helpers/mock.js
View file

@ -139,4 +139,8 @@ exports.inject = (ergogen) => {
return `references ${p.ref_hide ? 'hidden' : 'shown'}`
}
})
ergogen.inject('template', 'template_test', params => {
return `Custom template override. The secret is ${params.custom.secret}.`
})
}

2
test/index.js
View file

@ -5,7 +5,7 @@ const glob = require('glob')
const u = require('../src/utils')
const a = require('../src/assert')
const ergogen = require('../src/ergogen')
require('./helpers/mock_footprints').inject(ergogen)
require('./helpers/mock').inject(ergogen)
let what = process.env.npm_config_what
const dump = process.env.npm_config_dump

13
test/pcbs/mock_footprints___pcbs_main.kicad_pcb
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@ -1,5 +1,5 @@
(kicad_pcb (version 20171130) (host pcbnew 5.1.6)
(page A3)
@ -92,12 +92,12 @@
(outputdirectory ""))
)
(net 0 "")
(net 0 "")
(net 1 "P1")
(net 2 "T4_1")
(net 3 "T4_2")
(net 4 "T4_3")
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
@ -112,7 +112,7 @@
(add_net "T4_3")
)
(module trace_test (layer F.Cu) (tedit 5CF31DEF)
@ -234,7 +234,7 @@
)
(gr_line (start -9.5 9.5) (end 9.5 9.5) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start -9.5 9.5) (end 9.5 9.5) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 9.5 9.5) (end 9.5 -9.5) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 9.5 -9.5) (end -9.5 -9.5) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start -9.5 -9.5) (end -9.5 9.5) (angle 90) (layer Edge.Cuts) (width 0.15))
@ -242,7 +242,6 @@
(gr_line (start 29.5 9.5) (end 29.5 -9.5) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 29.5 -9.5) (end 10.5 -9.5) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 10.5 -9.5) (end 10.5 9.5) (angle 90) (layer Edge.Cuts) (width 0.15))
)

6
test/pcbs/mock_template.yaml Normal file
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@ -0,0 +1,6 @@
points.zones.matrix:
pcbs:
main:
template: template_test
params:
secret: 42

1
test/pcbs/mock_template___pcbs_main.kicad_pcb Normal file
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@ -0,0 +1 @@
Custom template override. The secret is 42.

13
test/pcbs/outlines___pcbs_main.kicad_pcb
View file

@ -1,5 +1,5 @@
(kicad_pcb (version 20171130) (host pcbnew 5.1.6)
(page A3)
@ -92,8 +92,8 @@
(outputdirectory ""))
)
(net 0 "")
(net 0 "")
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
@ -104,8 +104,8 @@
(add_net "")
)
(gr_line (start -5.7 9.5) (end 5.699999999999999 9.5) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start -5.7 9.5) (end 5.699999999999999 9.5) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 9.5 5.7) (end 9.5 -5.699999999999999) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 5.699999999999999 -9.5) (end -5.7 -9.5) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start -9.5 -5.699999999999999) (end -9.5 5.7) (angle 90) (layer Edge.Cuts) (width 0.15))
@ -126,7 +126,6 @@
(gr_line (start 14.25 0) (end 19 -4.75) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 19 -4.75) (end 23.75 0) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 23.75 0) (end 19 4.75) (angle 90) (layer Edge.Cuts) (width 0.15))
)

13
test/pcbs/references___pcbs_hidden.kicad_pcb
View file

@ -1,5 +1,5 @@
(kicad_pcb (version 20171130) (host pcbnew 5.1.6)
(page A3)
@ -92,8 +92,8 @@
(outputdirectory ""))
)
(net 0 "")
(net 0 "")
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
@ -104,9 +104,8 @@
(add_net "")
)
references hidden
references hidden
)

13
test/pcbs/references___pcbs_shown.kicad_pcb
View file

@ -1,5 +1,5 @@
(kicad_pcb (version 20171130) (host pcbnew 5.1.6)
(page A3)
@ -92,8 +92,8 @@
(outputdirectory ""))
)
(net 0 "")
(net 0 "")
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
@ -104,9 +104,8 @@
(add_net "")
)
references shown
references shown
)